1. Field of the Invention
The present invention generally relates to integrated circuit devices, and more particularly to a semiconductor chip and a complementary metal oxide semiconductor (CMOS) device having a both pure polysilicon and pure metal gates.
2. Description of the Related Art
Polysilicon is the standard gate material used for CMOS devices. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. Advantages of using polysilicon gates are that they can sustain high temperatures. Further, with the invention, the source/drain and gate can be doped and then silicided simultaneously in a self-aligned manner. Also, the mid-gap work function for a AMOS and n-MOS can be achieved, with the invention.
However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect and relative high electrical sheet resistance (approximately 150 Ohms/Sq.), dual poly-gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with poly gates is that the dopant in the poly-gate, such as boron, can easily diffuse through the thin gate dielectric causing further degradation of the device performance.
In the past, it has been a great challenge to form metal gates for CMOS devices in a dual metal gate structure because the integration process steps are complex and the processing costs are high. Conventional approaches of using tungsten to form the mid-gap metal gates for PFETs and NFETs have resulted in simpler processes. However, these approaches have failed to achieve the needed small threshold voltage. While counter doping the substrate and well can offset this requirement, doing so will negatively affect the short-channel characteristic of the device. An interim solution is taught in U.S. Pat. No. 6,049,114, xe2x80x9cSemiconductor Device Having a Metal Containing Layer Overlaying a Gate Dielectric,xe2x80x9d the complete disclosure of which is herein incorporated by reference, which discloses using layers of metal silicide to control the work function and to provide a lower resistance gate contact.
Some conventional solutions suggest using molybdenum as the gate metal and using a nitrogen ion-implant to tailor its work function, as described in xe2x80x9cNew Paradigm of Silicon Technologyxe2x80x9d, Tadahiro Ohmi, et al., Proceedings of the IEEE, Vol. 89, No. 3, March 2001, pp. 394-412, the complete disclosure of which is herein incorporated by reference. Furthermore, a technique disclosed in xe2x80x9cDual-Metal Gate CMOS Technology with Ultrathin Silicon Nitride Gate Dielectricxe2x80x9d, Yee-Chia Yeo, et al., IEE Electron Device Letters, Vol. 22, No. 5, May 2001, pp 227-229, the complete disclosure of which is herein incorporated by reference, teach how to make a low work function compound by co-evaporating silicon and alkali metal in an oxygen environment.
There are also some conventional methods that teach selectively plating a metal gate electrode. For example, one method for selectively plating a metallic film on a dielectric layer is disclosed in U.S. Pat. No. 3,011,920, xe2x80x9cMethod of Electroless Deposition on a Substrate and Catalyst Solution Thereforexe2x80x9d, the complete disclosure of which is herein incorporated by reference, which teaches sensitizing the substrate with a solution of a colloidal metal, accelerating the treatment with a selective solvent to remove protective colloids for the sensitized dielectric substrate, and then electrolessly depositing a metal coating on the sensitized substrate.
Also, other methods suggested in U.S. Pat. No. 3,099,608, xe2x80x9cMethod of Electroplating on a Dielectric Base;xe2x80x9d U.S. Pat. No. 4,569,743, xe2x80x9cMethod and Apparatus for the Elective, Self-Aligned Deposition of Metal Layers;xe2x80x9d and U.S. Pat. No. 6,153,935, xe2x80x9cDual Etch Stop/Diffusion Barrier for Damascene Interconnections,xe2x80x9d the complete disclosures of which are herein incorporated by reference, disclose that a dielectric layer can be pretreated by depositing a thin film conductive-type metal such as palladium, rhodium, ruthenium, molybdenum, indium, tin, or aluminum to provide a conducting base which permits electroplating with a conductive metal such as copper, gold, chromium, silver, cobalt, or nickel on the conductive base. As taught in U.S. Pat. No. 6,153,935, in certain cases, a diffusion barrier can be deposited after the conducting base and the conductive metal in order to prevent interactions between the conductive base and the conductive metal. Typical conductive metal diffusion barriers include Nixe2x80x94P, Coxe2x80x94P, Nixe2x80x94B, Coxe2x80x94B, Pd, Co(W)P, and Co(W)B. These diffusion barriers have excellent diffusion barrier properties and excellent adhesion to dielectric materials.
However, none of the prior art solutions teach a method of forming both pure polysilicon and pure metal gates on the same chip. Moreover, none of the prior art techniques provide a solution where one part of the chip can use a reliable, high-yield polysilicon gate, while the other part of the chip can use a high-performance, short channel metal gate.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional semiconductor integration processes the present invention has been devised, and it is an object of the present invention to provide a structure and method for a semiconductor chip that has both pure polysilicon and pure metal gate devices. It is another object of the present invention to provide a simple processing procedure to co-process polysilicon and metal gate devices on the same chip. Another object of the present invention is to share multiple processing steps when forming such devices using two different gate materials. Yet another object of the present invention is to provide a self-aligned, high-resolution, selective metal plating technique to form a metal gate after completion of the high-temperature processing steps. Still another object of the present invention is to provide a method of forming both a polysilicon gate and metal gate on the same integrated circuit chip. It is another object of the present invention to provide a solution where one part of the chip can use a reliable, high-yield polysilicon gate, while the other part of the chip can use a high-performance, short channel metal gate.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention, a method of forming semiconductor transistors having both metal gates and polysilicon gates on a single substrate in a single process. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate.
Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures. Then, the invention protects the polysilicon gates, removes the sacrificial polysilicon structures, and plates the metal gate seed areas to form the metal gates. The sidewall spacers self-align the metal gates. The plating process forms the metal gates of pure metal. All thermal processing that raises the temperature above a damage threshold for the metal is performed before the plating process.
This process produces a structure having a substrate having a first region and a second region, a metal gate transistor in the first region (the metal gate transistor having a pure metal gate) and a polysilicon gate transistor in the second region (the polysilicon gate transistor having a polysilicon gate). The metal gate transistor comprises an oxide layer above the substrate, a metal seed layer above the first oxide layer, and the pure metal gate above the metal seed layer. The pure metal gate comprises one of copper, gold, chromium, silver, cobalt, and nickel. The metal seed layer comprises metals in the class of ruthenium. The polysilicon gate transistor comprises an oxide layer above the substrate and a polysilicon gate above the oxide layer.
Thus, according to the present invention, polysilicon gate devices are formed in areas where reliability is more important than the performance and, in the same manufacturing process, metal gates are formed in areas where performance is paramount. An example of an area where reliability is most important is an embedded system containing a CPU macro and a memory macro. Here, it is important that the memory macro should have a high reliability in terms of yield, leakage level, radiation effect, etc. For example, the transfer gate of a DRAM cell has a polysilicon gate to ensure a low leakage current, so that retention time of the cell will meet design specifications. On the other hand, the CPU circuits could enjoy high-performance by using very short channel metal gates operated at low voltage. Thus, according to the present invention, a set of processing steps is disclosed which minimizes the process complexity and results in an overall lower processing cost compared with conventional techniques.
There are several benefits of the present invention. For example, the present invention provides a simple processing procedure to co-process polysilicon and metal gate devices on the same chip. The present invention also provides the ability to share multiple processing steps when forming such devices using two different gate materials. The present invention provides a self-aligned, high-resolution, selective metal plating technique to form a metal gate upon completion of the high-temperature processing steps. Thus, the present invention provides a solution where one part of the chip can use a reliable, high-yield polysilicon gate, while the other part of the chip can use a high-performance, short channel metal gate.